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? semiconductor MSM7503 1/41 ? semiconductor MSM7503 multi-function pcm codec general description the MSM7503 is a high performance, low power codec lsi device integrating a 2-wire time division transmission (ping-pong transmission) interface function and has a basic function of man-machine interface to that of the msm7502. the MSM7503 operates from single 5 v power supply and is ideal for digital telephone terminals such as pushbutton telephone sets and digital pbxs. the MSM7503 ping-pong transmission interface supports a bidirectional communication of up to 800 m long on the 2-wire twisted pair line, and can send and receive voice data at 64 kbps and control data at 16 kbps. the man-machine interface consists of analog speech path, key-scanner, tone generators, codec meeting the m /a companding law, and processor interface, which are controlled via 8- bit data buses. features ? single +5 v power supply ? low power dissipation power on mode : 50 mw typ. 100 mw max. power down mode : 15 mw typ. 30 mw max. ? pin-pong transmission : burst of 8 khz, transmission of 256 kbps, ami coding, 2-wire time division transmission ? transmission data configuration : transmit start bit (1 bit), k-bit (1 bit), control bit (2 bits), voice bit (8 bits), dc balance bit (1 bit), totalling 13 bits receive sync bit (4 bits), k-bit (1 bit), control bit (2 bits), voice bit (8 bits), dc balance bit (1 bit), totalling 16 bits ? control data interface supports synchronous and asynchronous communications ? built-in power-on reset by the power supply voltage monitoring ? output of the ping-pong transmission monitoring signal ? codec complied by the itu-t companding law ? calling tone interval : controlled by processor ? calling tone combination : controlled by processor, 6 modes ? calling tone volume : controlled by processor, 4 modes ? ringing tone interval : controlled by processor ? ringing tone frequency : controlled by processor, 6 modes ? ringing tone level : controlled by processor, 4 levels ? built-in pb tone generator ? built-in speech path control switches ? general latch output for external control : 2 bits ? watch-dog timer : 500 ms e2u0024-16-x2 this version: jan. 1998 previous version: nov. 1996
? semiconductor MSM7503 2/41 ? scanning i/o output : 8 bits input : 8 bits ? direct connection to handset : 1.2 k w driving available ? built-in pre-amplifier for loud-speaker ? hand-free interface ? m -law/a-law switchable codec ? lcd deflection angle voltage : controlled by processor, 8 levels ? package: 80-pin plastic qfp (qfp80-p-1420-0.80-bk) (product name : MSM7503gs-bk)
? semiconductor MSM7503 3/41 block diagram communication suppervisor r ? mix transmit polarity definition t ? counter start-stop sampling i/o clk t ? mix i/o intf crystal oscillator reset voltage detect vol9 r1n ps + + - - - - 1024 khz 20 db - - div pb gen. r tone gen. 400 425 440 450 400 16 400 20 f tone gen. 1 khz s tone gen. latch vlcd gen. ain pcmout aout pcmin m/a codec processor intf 8 khz man-machine intf scanning output scanning input start bit detector vol8 vol10 vol1 vol2 -8.7 db 0 db vol7 sw3 sw4 sw17 sw14 sw13 sw1 sw2 sw7 sw16 0 db 5.7 db vol3 vol4 sw12 sw5 sw5 0 db -3 db sw6 sw8 -6.8 db sw18 sw10 vol6 vol5 0 db vol11 vol12 sw21 sw15 sw11 sw20 sw19 vol13 sg gen. r2n t1n t2n xout x1 x2 test mpao mpai tpao tpai mpbo mpbi tpbi mldyi cao r1i r2i rpo rmi rmo0 rmo1 spi spo sa0 va vd ag dg sgt sgc po0~po7 pi0~pi7 sync clk1 clk2 clk3 clc fhw fd fk bhw bd bds ctest lrstn to cai wrn rdn cen db0 to db7 ad0 ad1 la lb vlcd 64 khz wdt output + 0 db sw9 0 db - -
? semiconductor MSM7503 4/41 pin configuration (top view) 1 24 64 41 clk2 clk1 sync fhw bhw ctest lrstn lb la sao vlcd dg rmo1 rmo0 rmi spi spo rpo r2i r1i mpbo cen rdn wrn ad1 ad0 db7 db6 db5 db4 db2 db1 pi7 pi6 pi5 pi4 pi3 pi2 pi1 pi0 po1 db0 po0 mpai tpbi tpai sgt to va sgc po7 po4 fk clc bd ps t2n t1n r1n xout x1 fd clk3 r2n bds test x2 vd 80-pin plastic qfp ag mldyi mpbi mpao tpao cai cao po6 po5 po3 po2 db3 2 3 4 5 6 7 8 9 10 11 12 14 15 16 17 18 19 20 21 23 13 22 63 62 61 60 59 58 57 56 55 54 53 51 50 49 48 47 46 45 44 42 52 43 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40
? semiconductor MSM7503 5/41 pin and functional descriptions la, lb general latch outputs for external control. statuses of these outputs are controlled via the processor interface. refer to the description of the control data for details. these outputs provide the capability to drive one ttl. dg digital ground. dg is separated from the analog ground ag inside the device. but, dg should be connected as close to the ag pin on pcb as possible. ag analog ground. sa0 sounder (calling tone) driving outputs. through processor control, the calling tone volume is selectable from 4 levels and one of six tone combinations is selectable. initially, the calling tone volume is set at a maximum and the tone combination is set at a 16 hz wamble tone by a combination of 1 khz and 1.3 khz. the sa0 outputs pulse waveforms using dg as a reference potential.
? semiconductor MSM7503 6/41 rmi, rmo0, rmo1 receive main amplifier input and outputs. rmi is the inverted input and rmo0 and rmo1 are the outputs of the receive main amplifier. the output signal on rmo1 is inverted against rmo0 by a gain 1 (0 db), so the earphone of a handset is directly connected between rmo0 and rmo1. during the system power down, the rmo0 and rmo1 outputs are in a high impedance state. the receive main amplifier gain is determined by a resistor connected between rpo and rmi, and a resistor connected between rmi and rmo0. the receive main amplifier gain varies between 0 and +20 db in effect. a piezo- receiver with an impedance greater than 1.2 k w is available. if the adjusting of receive path frequency characteristics is required, insert the following circuit for adjustment. during the whole system power on, the speech path from rmi to rmo0 and rmo1 is disconnected and the output of rmo0 and rmo1 is at the sg level (va/2). the speech path is provided by processor control. a circuit example for adjustment of frequency characteristics rpo rmi r1 rmo0 main amplifier gain without capacitors g= r2 r1 c1 r2 c2 spi addition input of speaker amplifier. the typical gain between spi and spo is 0 db. but, the 2-stage gain amplifier allows to set up a gain between 0 db and C18 db in a 6 db step, or a gain between 0 db and C28 db in a 4 db step through processor control. the input resistance of spi is typically 20 k w to 150 k w (it varies by gain setting).
? semiconductor MSM7503 7/41 spo output of pre-amplifier for speaker. since the driving capability is 2.4 v pp for the load of 20 k w , spo can not directly drive a speaker. during the whole system power down mode, spo is at an analog ground level. during the whole system power on mode, spo is in a non-signal state (sg level), and a receive voice signal, r-tone, f-tone, hold acknowledge tone, pb signal acknowledge tone, and sounder tone are output from the speaker by processor control. when the speaker is used as a sounder, the sounder tone is output via the spo pin by connecting the spi input with the sounder output (sa0 or sa1). in addition, when the ad-converted sounder tone is sent from the main device, the sounder tone is output via the spo pin since the cao pin for codec output is internally connected. r1i, r2i, rpo r1i and r2i are for the inputs and rpo is for the output of the receive pre-amplifier. normally, r1i is connected via an ac-coupling capacitor to the codec analog output (cao), and r2i is used as the mixing signal input pin. the typical gain between r1i and pro is C6 db. through processor control, gains are variable from C14 db to 0 db in 2 db steps. in addition, the receive pad can control the gain of C9, C6, C3, or 0 db. the gain between r2i and rpo is fixed to 0 db. during the whole system power-on mode, the rpo output is in non-signal state, and speech signal, r-tone, f-tone, pb acknowledge tone, side tone signal are output by processor control. during the whole system power-down mode, the rpo output is the analog ground level. the input resistance of r1i is typically between 20 k w and 100 k w (it varies by gain setting). the input resistance of r2i is typically 20 k w . mldyi hold tone signal input. for example, the output of external melody ic is connected to this pin. through processor control, the signal applied to mldyi is output from the to output pin as a hold tone on the transmit path, and from the spo output pin as a hold acknowledge tone on the receive path. the typical gain between mldyi and to is C2 db. through processor control, a gain between C2 db and C11 db is also settable at 3 db steps. the typical gain between mldyi and spo is C3 db. through processor control, a gain between C3 db to C31 db is also settable at 4 db steps. mldyi is a high impedance input, so insert an about 100 k w bias resistor between mldyi and sgt.
? semiconductor MSM7503 8/41 tpbi, to tpbi is the input and to is the output of the transmit pre-amplifier (b). when the handset is used, tpbi is connected to the transmit pre-amplifier (a) output pin (tpao). if adjustment of frequency characteristics on the transmit path is required, insert a circuit for adjustment of characteristic between tpao and tpbi. through processor control, the signal applied to this pin is output via the to pin on the transmit path and its side tone via the rpo pin. during the whole system power down mode, to is at an analog ground level. the typical gain between tpbi and to is +17.7 db. through processor control, a gain between +17.7 db and +8.7 db is also settable at 3 db steps. the typical gain between tpbi and rpo is +3.0 db. through processor control, a gain between C9 db and +9 db is variable in 3 db steps. changing the gain between tpbi and to may change the gain between tpbi and rpo. tpbi is a high impedance input, so insert an about 100 k w resistor between tpbi and sgt. tpao tpbi sgt c3 r3 c4 r4 a circuit example for adjustment of frequency characteristics mpai, mpao handfree microphone pre-amplifier (a) input and output. mpai is the input and mpao is the output. the speech path between mpai and mpao is always active regardless of processor control. during the whole system power saving mode, mpao is at an analog ground level. the gain between mpai and mpao is typically +20 db. through processor control, gains between +14 db and +11 db are also settable. mpai is a high impedance input, so insert an about 100 k w between mpai and sgt. mpbi, mpbo the handfree microphone (b) input and output. mpbi is the inverted input and mpbo is the output. with an external resistor, the amplifier gain is adjusted in the range between C25 db and +25 db. a signal on the mpbo is output via the to pin through processor control. during the whole system power down mode, mpbo is at an analog ground level. the gain between mpbo and to is fixed to 0 db.
? semiconductor MSM7503 9/41 tpai, tpao the transmit pre-amplifier (a) input and output. tpai is the input and tpao is the output. tpai should be connected to the microphone of handset via an ac-coupling capacitor if the dc offset appears at a transmit signal (offset from sgt). the transmit path from tpai to tpao is always active regardless of processor control. during the whole system power down mode, tpao is at an analog ground level. the gain between tpai and tpao is fixed to 20 db. sgt transmit path signal ground. sgt outputs half the supply voltage. during the whole power down mode, sgt output is in a high impedance state. sgc bypass capacitor connecting pin for a signal ground level. insert a 0.1 m f high performance capacitor between sgc and ag. va, vd +5 v power supply. va is for an analog circuit and vd is for a digital circuit. both va and vd should be connected to the +5 v analog path of the system. cai, cao codec analog input and output. cai is the analog input of codec to be connected to the to pin. if the dc offset voltage on the to signal is great, cai should be connected via ac-coupling capacitor. at this time, insert an about 100 k w bias resistor between cai and sgt. cao is the analog output of codec. cao should be connected to r1i via ac-coupling capacitor. a bias resistor is not required to r1i. during the whole system or codec power down mode, cao is at the sg voltage level.
? semiconductor MSM7503 10/41 po0, po1, po2, po3, po4, po5, po6, po7 scanning outputs. these output pins need external pull-up resistors because of their open- drain circuits. but, when these are used in combination with pi0 to pi7, pull-up resistors are not required. through processor control, these outputs can be set open or to digital "0". initially, these outputs are set at an opened state. pi0, pi1, pi2, pi3, pi4, pi5, pi6, pi7 scanning inputs. in the read mode, data on pi0 to pi7 can be read out of the processor via data bus (db0 to db7). since these inputs are pulled up inside the ic, external resistors are not required. db0, db1, db2, db3, db4, db5, db6, db7 data bus i/o pins. these pins are configured as an output during the read mode only and as an input during other modes. t1n, t2n line transmit signal output. signals which consist of a total of 13 bits configured by the start bit (fixed at "1"), the k bit (fixed at "1"), the d bits (control data of two bits), the transmit b bits (eight for voice and data) and the dc bit (1 bit for the dc balance) at the bit rate of 256 khz are output in burst mode from the t1n pin and the t2n pin in turn at intervals of 125 m sec. these output signals become the ami code with a duty of 50% in the line coding configuration by connecting to the line via a transformer etc. in the output timing of the t1n and t2n pins, the top bit of the signal is output after receiving a 16-bit signal. r1n, r2n line receive signal input. line signals (50% duty ami code) which consist of a total of 16 bits configured by the frame synchronous bits (four bits with "1"), the k bit (one bit for polling), the d bits (control data of two bits), the receive b bits (eight bits for voice and data), and the dc bit (bit for dc balance) have been transmitted in burst mode at the bit rate of 256 khz at interval of 125 m sec. these signals should be input in the r1n pin and the r2n pin after separating then into the polarity of "+" and "C".
? semiconductor MSM7503 11/41 sync synchronous signal (8 khz) output. this synchronous signal is generated by dividing the oscillator output of 8.192 mhz, applying the frame synchronous bit included in the line signal as a reference phase. this signal also sent to the tone generator and the codec inside the device. all timing signals of the codec are synchronized by this signal. clk1 64 khz clk signal output synchronized to the sync signal output. this signal is connected to the codec inside the device and is used as a bit clock for receiving and sending the pcm i/o data from and to the ping-pong transmission interface. when an external signal is input to the bhw pin, or when the fhw pin outputs signals for the external circuit, the timing should be set by the clk1 signal. this signal is always output in the power on mode. clk2 16 khz clk signal output synchronized to the sync signal output. this signal can be used for the input or output of the control signal (bd input or fd output) of 16 kbps. this signal is always output in the power on mode. clk3 clk signal output of 256 khz synchronized to the sync signal. this signal can be used when the control signal of 16 khz is input or output from or to the external device by the start-stop synchronization. this signal is always output in the power on mode. clc control signal input for phase-inverting the 256 khz clk signal which is output form the clk3 pin. if the reference phase is set by setting clc to "0", the clk signal of 256 khz is phase-inverted against the reference phase by setting clc to "1".
? semiconductor MSM7503 12/41 fhw the output of the extracted b-bit (8-bit sequence) from receive signals which are input to r1n and r2n. this signal is output synchronizing to the rising edge of a clk1 (64 khz) output signal beginning with the rising edge of a sync output signal. since this pin is connected to the d/a converter of the codec inside device, the b bits of receive signals are decoded to analog signals. bhw input to the b bit slot of line signals transmitted from the t1n and t2n pins. the input signal to this pin must be synchronized to the clk1 output signal (64 khz) beginning with the rising edge of the sync output signal. the input signal is shifted at the falling edge of clk1. in the case of inserting the voice data into the transmit b bit, the pcm output of the codec is connected to this input pin, and inserting the voice data into the b bit slot is enabled by setting sw12 to on through processor control. in this case the bhw pin is used as an output pin, so external signals can not be input to this pin. this is an input and output pin of an open drain type with a pulled-up resistance of 5 k w . fd the signal output of the extracted control bit (2-bit sequence at 16 kbps) from line signals which are input to the r1n and r2n pins. this signal is output synchronizing to the rising edge of a clk2 output signal beginning with the rising edge of the sync output signal. fd is an output pin of an open drain type with a pulled-up resistance of about 10 k w . fk the signal output of the extracted k bit (8 kbps) from the line receive signals which are input to the r1n and r2n pins. this signal is output synchronizing to the rising edge of a sync output signal. fk is an output pin of an open drain type with a pulled-up resistance of about 10 k w .
? semiconductor MSM7503 13/41 bd input to the d bit (2-bit sequence at 16 kbps) of line signals transmitted from the t1n and t2n pins. when the bds control pin is in "0", this pin enters the synchronous mode and data must be input to this pin synchronizing with clk2 (16 khz). when the bds control pin is set to "1", this pin enters the asynchronous data input mode and the asynchronous data of 11 bits including the start bit and stop bit can be input at data rate of 16 kbps. bds control signal input for selection of the synchronous mode or asynchronous mode for control data (d-bit) input. when being at "0" level, this pin enters the synchronous data input mode, when being at "1" level, this pin enters the asynchronous data input mode. ps monitoring signal output for the state of the ping-pong transmission. when frames are synchronized (in normal operation) after receiving more than three consecutive frame synchronous signals which are included in the line receive signal sequence, this pin outputs "1". otherwise, this pin outputs "0". ps is an output of an open drain type with pulled-up resistance of about 10 k w . x1, x2 clk oscillator circuit input and output. x1 is input and x2 is output. a crystal oscillator of 8.192 mhz should be connected between x1 and x2. if the frequency deviation in clk oscillation is great with respect to the receive data rate, the noise of the codec increases. the oscillation frequency deviation in clk should be kept in 20 ppm or less.
? semiconductor MSM7503 14/41 xout 8.192 mhz clk signal output. if capacitance load is given to the output, the current consumption will increase. about 0.03 ma/ pf. ad0, ad1 address data inputs for the internal control registers. addressing of the internal control registers is executed by ad0 and ad1 and sub address data, db7 and db6. wrn write signal for internal control registers. data on the data bus is written into the registers at the rising edge of wrn under the condition of digital "0" of cen (chip enable). while cen is in digital "1" state, wrn becomes invalid. the write cycle is a minimum of 2 m s regardless of the presence or absence of clock signals. ad1 ad0 db7 db6 function 00 0 0 on/off controls of sounder, r-tone, f-tone 0 1 level/frequency controls of sounder, r-tone 1 0 pb tone control 11 controls of internal speech path switch and general latch watchdog timer reset 0 0 controls of receive gain and side tone gain 0 1 controls of transmit hold tone, pb tone, handfree input, handset inputs gain 1 0 controls of speaker pre-amplifier gain and additional speaker gain 1 1 controls of receive pad and incoming tone input gain 01 1 0 scanning output control 1 1 0 0 scanning interrupt reset 1 1 0 1 lcd deflection angle control voltage setting 1 1 1 0 power on/off control 1 1 1 1 codec control (controls of companding law and digital loop) 1 0 scanning data read-out write read
? semiconductor MSM7503 15/41 rdn read signal input to read pi0 to pi7 out of the processor. when cen and rdn are in digital "0" state, the digital values on pi0 to pi7 are output onto the data buses db0 to db7. while cen is in digital "1" state, the rdn signal becomes invalid. cen chip enable signal input. when cen is in digital "0" state, wrn and rdn are valid. vlcd by processor control, vlcd outputs a dc voltage between 0 and 1.4 v is about 0.2 v step. this is used to control the deflection angle of the lcd display. vlcd has the internal resistance value of about 1 k w , so the external load of over 100 k w should be used. during initialized state, vlcd outputs the voltage of 0 v. lrstn reset signal output for external circuit. this reset signal output pin goes to "0" level when the power supply is approximately more than 4.0 v or when the test pin is at digital "0" level and the watchdog timer (wdt) outputs a signal. the wdt output does not affect the lsrtn output when test pin is at digital "1" level. the lrstn signal is also used as a reset signal for internal registers. when lrstn is at "0" level, all internal control registers are initialized. the internal wdt outputs a 500 ms cycle signal when the lrstn is at digital "1" and the processor does not send a timer reset signal. refer to the figure 1 for the output timing of this output. test control signal input for deciding valid/invalid of reset control from the internal wdt output. when this input pin is at digital "0" level, the lrstn output goes to "0" level. when this input pin is at "1" level, the internal wdt does not affect the lsrtn output. ctest test pin for shipment testing. this pin should be set to "0" level.
? semiconductor MSM7503 16/41 absolute maximum ratings parameter symbol condition rating unit power supply voltage v dd 0 to 7 v analog input voltage v ain C0.3 to v dd + 0.3 digital input voltage v din C0.3 to v dd + 0.3 storage temperature t stg -55 to 150 ag, dg = 0 v ag, dg = 0 v ag, dg = 0 v v c v recommend operating conditions (analog interface) r al tpao, mpao, mpbo, to, 20 analog load resistance k w rmo0, rmo1 with respected to 0.6 c al tpao, mpao, mpbo, to, rpo, spo, cao 30 analog load capacitance rmo0, rmo1 70 pf nf tpai, tpbi, mpai C10 10 mldy C50 50 r1i, r2i, spi C25 25 cai C100 100 allowable analog input offset voltage v off mv min. max. parameter symbol condition typ. unit sg level rpo, spo, cao with respect to sg input high voltage v d va, vd (voltage must be fixed) 5.0 4.75 5.25 ta 25 C10 70 power supply voltage v v ih all digital input pins 2.2 v dd v input low voltage v il all digital input pins 0 0.8 v operating temperature range c digital input rise time t ir all digital input pins 50ns digital input fall time t if all digital input pins 50ns po0 to po7 10 digital output load r dl k w po0 to po7 100 c dl pf min. max. parameter symbol condition typ. unit other digital output pins except po0 to po7 10 oscillating frequency allowable frequency deviation temperature characteristics equivalent series resistance production load capacitance crystal oscillator C50 C50 8.192 16 50 50 80 mhz ppm ppm w pf 25c 3c recommended operating conditions
? semiconductor MSM7503 17/41 recommended operating conditions (processor digital interface) p w write pulse period ns wrn 2000 t w write pulse width ns wrn 100 t r read pulse width ns rdn 200 ad0, ad1 ? wrn ns 80 t aw1 ad0, ad1 ? rdn ns 80 t ar1 address data setup time wrn ? ad0, ad1 ns 50 t aw2 rdn ? ad0, ad1 ns 50 t ar2 address data hold time cen ? wrn ns 80 t cw1 cen ? rdn ns 80 t cr1 cen setup time wrn ? cen ns 50 t cw2 rdn ? cen ns 50 t cr2 cen hold time db0 to 7 ? wrn data setup time ns 110 t dw1 wrn ? db0 to 7 data hold time ns 20 t dw2 see fig.2 min. max. parameter symbol condition typ. unit recommended operating conditions (ping-pong transmission interface) t sbhw b signal set-up time ns bhw input 50 see fig. 5 t hbhw b signal hold time ns bhw input 50 t sbd d signal set-up time ns bd input 50 t hbd d signal hold time ns bd input 50 t cb receive data cycle time m s r1n, r2n 3.906 t wb receive data width m s width of "l" at r1n and r2n 1.953 1.35 2.5 t fm receive flame cycle time m s 125 see fig. 5 see fig. 5 see fig. 4 see fig. 4 see fig. 3 see fig. 3 min. max. parameter symbol condition typ. unit
? semiconductor MSM7503 18/41 electrical characteristics dc and digital interface characteristics i dd1 operating mode (no signal, sounder off) 10 20 power supply current ma (v dd = 5 v 5%, ta = C10c to 70c) i dd2 whole system power down 3 6ma i dd3 codec power down 7 14ma input high voltage v ih 2.2 v dd v input low voltage v il 0.0 0.8 v digital pins except for pi0 to pi7 2.0 m a i ih pi0 to pi7 (internal pull-up pins) 2.0 m a high input leakage current digital pins except for pi0 to pi7 0.5 m a i il pi0 to pi7 (internal pull-up pins) 10 25 m a low input leakage current output pins 1 *1 i oh = 0.1 ma output pins 2 *2 i oh = 1.6 ma 2.4 2.4 digital output high voltage v oh v i ol = C1.6 ma 0.0 digital output low voltage v ol 0.4 v db0 to db7 (write mode) digital output leakage current i o 10 m a tpao, mpao analog output offset voltage v off C200 200 input capacitance c in 5 pf tpai, tpbi, mldyi, rmi, mpai, mpbi 10 m w r1i, r2i, spi 10 k w cai (fin : < 4 khz) 1 m w analog input resistance r in va/2 C0.05 va/2 +0.05 sg voltage va/2 v i sgf force current 1.5 1.0 i sgs sink current 0.5 0.3 sg drive current ma equivalent pull-up resistance r pull pi0 to pi7, v i = 0 v 370 200 500 k w v dd v dd min. max. parameter symbol condition typ. unit power supply voltage detection v th power supply voltage at lrstn = 1, see fig. 1 3.9 v power supply voltage non-detection v tl power supply voltage at lrstn = 0, see fig. 1 3.8 v all output pins i oh = 1 m a 3.8 v pp C100 100 mv mpbo, to, cao, rpo, rmo0, rmo1, spo notes: *1 bhw, fk, fd, ps *2 sync, clk1, clk2, clk3, t1n, t2n, xout, la, lb, lrstn, db0 to db7
? semiconductor MSM7503 19/41 digital interface characteristics parameter symbol condition typ. unit min. max. t pd la 0.2 1.5 digital output (latch) delay time m s (v dd = 5 v 5%, ta = C10c to 70c) t pd scn wr ? po0 to po7 0.2 1.5 key scanning output delay time m s t pd data 20 10 100 digital output (data) delay time ns t drst1 lrstn 0 ? 1 128 delay time of power supply voltage detect ms t drst2 lrstn 1 ? 0 0.01 m s t wdt 500 delay time of lrstn due to wdt ms t drst3 see fig. 1 0.85 m s t wrst 1.7 t dsck1 366 488 clk output delay time t ssck2 366 488 ns t dsck3 366 488 t dfhw 10 b signal delay time ns t dfd 340 d signal output delay time ns 10 t dfk 740 k signal output delay time ns 500 f sync 8 sync output frequency khz see fig. 1 sync ? clk1 sync ? clk2 sync ? clk3 see fig. 3 see fig. 4 clk1 ? fhw see fig. 3 clk2 ? fd see fig. 4 l ? h h ? l l ? h h ? l see fig. 4 t wsync 16.6 sync output width m s f clk1 64 clk1 output frequency khz f clk2 16 clk2 output frequency khz f clk3 256 clk3 output frequency khz clk1, clk2, clk3 50 clk output duty ratio % t wf t1n, t2n "l" width 1.953 line output signal width m s sync, clk1, clk2 250 clock output jitter width ns clk3 when use xtal pull-up resistance 10 k w wr ? la, lb rd ? db0~db7 see fig. 2 see fig. 2 see fig. 2 see fig. 5
? semiconductor MSM7503 20/41 ac characteristics 1 (codec) notes: *1 the psophometric weighted filter is used *2 pcmin input: idle code loss t1 loss t2 loss t3 loss t4 loss t5 loss t6 transmit frequency response db parameter symbol condition typ. unit min. max. freq. (hz) level (dbm0) 60 300 1020 2020 3000 3400 27 0.07 C0.03 0.06 0.38 20 C0.20 C0.15 C0.15 0.0 0.20 0.20 0.20 0.80 0 reference loss r1 loss r2 loss r3 loss r4 loss r5 300 1020 2020 3000 3400 C0.03 C0.02 0.15 0.56 C0.15 C0.15 C0.15 0.0 0.20 0.20 0.20 0.80 reference receive frequency response db 0 sd t1 sd t2 sd t3 sd t4 sd t5 43.0 41.0 38.0 31.0 26.5 35 35 35 29 24 db 1020 3 0 C30 C40 C45 transmit signal to distortion ratio *1 sd r1 sd r2 sd r3 sd r4 sd r5 43.0 41.0 40.0 34.0 31.0 37 37 37 30 25 db 1020 3 0 C30 C40 C45 receive signal to distortion ratio *1 gt t1 gt t2 gt t3 gt t4 gt t5 0.01 C0.05 0.05 0.30 C0.3 C0.3 C0.5 C1.2 0.3 0.3 0.4 1.2 reference transmit gain tracking db 1020 3 C10 C40 C50 C55 gt r1 gt r2 gt r3 gt r4 gt r5 0.0 C0.10 C0.30 C0.40 C0.3 C0.3 C0.5 C1.2 0.3 0.3 0.5 1.2 reference receive gain tracking db 1020 3 C10 C40 C50 C55 ain = sg *1 nidle t m a C73.5 C71 C70 C68 *1 *2 nidle r C78.0 C75 idle channel noise dbmop av t 0.5671 0.6007 0.6363 av r 0.5671 0.6007 0.6363 1020 0 vrms absolute amplitude cai ? cao bclock = 64 khz absolute delay time td 1020 0 0.58 0.60 ms (v dd = 5 v 5%, ta = C10c to 70c) cai ? bhw fhw ? cao
? semiconductor MSM7503 21/41 ac characteristics 1 (codec) (continued) notes: *3 the minimum value of group delay only is defined as the reference value *4 measurement at the idle channel noise t gd t1 t gd t2 t gd t3 t gd t4 t gd t5 transmit group delay ms 500 600 1000 2600 2800 0.19 0.12 0.02 0.05 0.08 0.75 0.35 0.125 0.125 0.75 0*3 t gd r1 t gd r2 t gd r3 t gd r4 t gd r5 receive group delay ms 500 600 1000 2600 2800 0.0 0.0 0.0 0.09 0.12 0.75 0.35 0.125 0.125 0.75 0*3 cr t cai ? cao 78 70 cr r fhw ? bhw cao left open 86 75 1020 0 crosstalk attenuation db 4.6 khz to 72 khz discrimination out-of-band signal dis 0 to 4000 hz C25 32.0 30 db 300 to 3400 out-of-band signal spurious s 4.6 khz to 100 khz 0 C37.5 C35 dbmo fa = 470 fb = 320 intermodulation distortion imd 2faCfb C4 C52 C35 dbmo psr t *4 30 25 psr r 0 to 50 khz 50 mv pp power supply noise rejection ratio db parameter symbol condition typ. unit min. max. freq. (hz) level (dbm0) (v dd = 5 v 5%, ta = C10c to 70c)
? semiconductor MSM7503 22/41 ac characteristics 2 (transmit path) gtpa pre-amp gain db 1020 C24.0 20.0 18.0 22.0 tpai-tpao tpbi-to set at typical gain gtpb1 transmit path gain db 17.7 15.7 19.7 C3 db C6 db C9 db setting, than typical gain rg1tpb rg2tpb rg3tpb C3.0 C6.0 C9.0 C5.0 C8.0 C11.0 C1.0 C4.0 C7.0 transmit path gain setting (vol8) db mpai-mpao set at typical gain gmpa db 20.0 18.0 22.0 microphone pre-amp gain setting, than typical gain C6 db C9 db rg1mpa rg2mpa C6.0 C9.0 C8.0 C11.0 C4.0 C7.0 db microphone pre-amp gain setting (vol9) 1020 C24.0 additional transmit signal gain gtmx 1020 C4.0 mpbo-to 0.0 C2.0 2.0 db to per wave set at typical gain in-channel pb signal output level vpbt1 C17.4 C19.4 C15.4 dbv C3 db C6 db C9 db setting, than typical gain gpbt1 gpbt2 gpbt3 C3.0 C6.0 C9.0 C5.0 C8.0 C11.0 C1.0 C4.0 C7.0 db in-channel pb signal output level setting (vol4) in-channel pb signal frequency deviation dfpbt C1.0 1.0 % mldyi-to set at typical gain hold tone path gain gpat 1020 C4.0 C2.0 C4.0 0.0 db C3 db C6 db C9 db setting, than typical gain rg1pat rg2pat rg3pat C3.0 C6.0 C9.0 C5.0 C8.0 C11.0 C1.0 C4.0 C7.0 db hold tone path gain setting (vol3) tpai:terminated in 510 w measured at to tpao-tpbi directly connected set at typical gain *5 idle channel noise nitpa C70 dbv tpao, to, mpao, mpbo r l = 20 k w maximum output voltage swing vot 1020 2.4 v pp in-channel pb signal distortion thdpbt in-band distortion C35 C30 db parameter symbol condition typ. unit min. max. freq. (hz) level (dbv) (v dd = 5 v 5%, ta = C10c to 70c) cross talk attennation at microphone signal path tmx off 1020 C24 mpai-to 60 50 db note: *5 noise band width: 0.3 to 3.4 khz, non weighted
? semiconductor MSM7503 23/41 ac characteristics 3 (receive path) receive signal path gain db 1020 C4.0 C6.0 C8.0 C4.0 typical gain is set between r1i and rpo receive signal path gain setting (vol1) db receive pad gain setting (vol10) db additional receive signal path gain grmx db 0.0 C2.0 2.0 r2i and rpo C4.0 1020 gside side tone path gain db 1020 C14.0 3.0 1.0 5.0 typical gain is set betweentpbi and rpo side tone path gain setting (vol2) db typical gain is set between rpo and spo speaker pre-amp gain gsp db 0.0 C2.0 2.0 1020 C4.0 speaker pre-amp gain setting (vol5) db additional speaker input path gain typical gain is set between spi and spo gspi db 0.0 C2.0 2.0 C4.0 1020 grpa C8 db C6 db C4 db C2 db 2 db 4 db 6 db setting, than typical gain rgrpa1 rgrpa2 rgrpa3 rgrpa4 rgrpa5 rgrpa6 rgrpa7 C8.0 C6.0 C4.0 C2.0 2.0 4.0 6.0 C10.0 C8.0 C6.0 C4.0 0.0 2.0 4.0 C6.0 C4.0 C2.0 0.0 4.0 6.0 8.0 setting, than typical gain C3 db C6 db C9 db C3.0 C6.0 C9.0 C5.0 C8.0 C11.0 C1.0 C4.0 C7.0 rgpad1 rgpad2 rgpad3 6 db 3 db C3 db C6 db C9 db C12 db setting, than typical gain rgside1 rgside2 rgside3 rgside4 rgside5 rgside6 6.0 3.0 C3.0 C6.0 C9.0 C12.0 4.0 1.0 C5.0 C8.0 C11.0 C14.0 8.0 5.0 C1.0 C4.0 C7.0 C10.0 C4 db C8 db C12 db C16 db C20 db C24 db C28 db setting, than typical gain rgsp1 rgsp2 rgsp3 rgsp4 rgsp5 rgsp6 rgsp7 C4.0 C8.0 C12.0 C16.0 C20.0 C24.0 C28.0 C6.0 C10.0 C14.0 C18.0 C22.0 C26.0 C30.0 C2.0 C6.0 C10.0 C14.0 C18.0 C22.0 C26.0 parameter symbol condition typ. unit min. max. freq. (hz) level (dbv) (v dd = 5 v 5%, ta = C10 to 70c)
? semiconductor MSM7503 24/41 ac characteristics 3 (receive path) (continued) gpar hold acknowledge tone path gain db C3.0 C5.0 C1.0 typical gain is set between mldyi and spo pb acknowledge tone output level dbv C10 db C20 db setting, than typical gain vpbrp C30.1 C32.1 C28.1 1020 C4.0 rpo per wave spo per wave set at typical gain dbv vpbsp C28.2 C30.2 C26.2 dfpbr pb acknowledge tone frequency difference % C1.0 1.0 rpo, spo thdpbr pb acknowledge tone distortion db C35 C30 rpo, spo typical gain is set between cao and spo incoming tone speaker output path gain gcao db 0.0 C2.0 2.0 1020 C20 incoming tone speaker output path gain setting (vol11) rgcao1 rgcao2 C10.0 C20.0 C12.0 C22.0 C8.0 C18.0 db r1i:sg, measured at rpo set at typical gain. nirpo dbv C86.0 r1i:sg, measured at spo set at typical gain. nispo dbv C89.0 r1i:sg, gain 0 db rmo0, rmob *5 nirmo dbv C86.0 idle channel noise rpo, spo rl = 20 k w vor maximum output amplitude v pp 2.4 parameter symbol condition typ. unit min. max. freq. (hz) level (dbv) (v dd = 5 v 5%, ta = C10c to 70c) additional speaker input path gain setting (vol6) C4.0 1020 rgspi1 rgspi2 rgspi3 setting, than typical gain C6 db C12 db C18 db C6.0 C12.0 C18.0 C8.0 C14.0 C20.0 C4.0 C10.0 C16.0 db vor maximum output amplitude v pp 3.6 resister of 1.2 k w between rmo0 and rmo1 measurement at each output 1020 rx to tx cross talk attennation between transmit path and receive path dbv 55 4.5 between r1i and to 1020 C4 note: *5 noise band width : 0.3 khz to 3.4 khz, non weighted
? semiconductor MSM7503 25/41 ac characteristics 4 (ringing tone) vrto r-tone output amplitude (vol7) mv pp 90 120 150 180 63 84 105 126 117 156 195 234 level setting 1 level setting 2 level setting 3 level setting 4 rpo vftrp rpo 160 112 208 vftsp spo 11.0 7.5 14.5 f-tone output amplitude mv pp 0 db C10 db C20 db gain setting 220 70 17 154 49 12 286 91 22 vstsp spo s-tone output amplitude (vol12) mv pp (v dd = 5 v 5%, ta = C10c to 70c) min. max. parameter symbol condition typ. unit d ft C0.5 C0.5 frequency deviation % ac characteristics 4 (sounder output circuit) lcd defelection angle control voltage output vlcd output voltage v 1.4 1.2 1.0 0.8 0.8 0.4 0.2 0.0 1.1 0.9 0.7 0.5 0.3 0.2 0.15 0.0 1.7 1.5 1.3 1.1 0.9 0.6 0.4 0.05 db2 1 1 1 1 0 0 0 0 db1 1 1 0 0 1 1 0 0 db0 1 0 1 0 1 0 1 0 output resistance rolcd 1.0 k w output load rllcd 100 k w to gnd (v dd = 5 v 5%, ta = C10c to 70c) min. max. parameter symbol condition typ. unit vst1 vst2 vst3 vst4 sounder tone output amplitude (vol13) v 4 1.2 0.44 0.27 3.5 1 0.25 0.2 1.5 0.6 0.35 vol.1 vol.2 vol.3 vol.4 reference level of dg rlsa0 is 40 k w or more. parameter symbol condition typ. unit min. max. freq. (hz) level (dbv) (v dd = 5 v 5%, ta = C10c to 70c) output resistance output load rosao rlsao with respect to dg k w k w 40 2
? semiconductor MSM7503 26/41 timing diagram reset signal output timing processor interface timing vd (va) v th td rst1 lrstn v th td rst1 v tl td rst2 (a) lrstn output timing by the power supply voltage charging writing the reset data of wdt internal wdt output t wdt td rst3 lrstn t wrst t wdt (b) lrstn output timing by the internal wdt figure 1 figure 2 ad0, ad1 cen wrn rdn db0 to db7 po0 to po7 latch output t cw1 t cw2 t w t pddata t pddata t pdscn t pdla t aw1 t aw2 t ar1 t ar2 t cr1 t cr2 t r t dw1 t dw2
? semiconductor MSM7503 27/41 b-bit signal i/o timing d-, k-bit signal i/o timing sync clk1 fhw output bhw input 1/f sync t wsync 1/f clk1 td sck1 td fhw f0 f1 f2 f3 f4 f5 f6 f7 f0 f1 b0 b1 b2 b3 b4 b5 b6 b7 b0 b1 t sbhw t hbhw figure 3 1/f clk2 td sck2 1/f clk3 td sck3 td fd td fd t sbd t hbd td fk sync clk2 clk3 (clc=1) clk3 (clc=0) fd output bd output fk output figure 4
? semiconductor MSM7503 28/41 ping-pong transmission signal timing 1 frame (tfm 125 m s) receive (62.4 m s) transmit (50.78 m s) twb tcb 1 1 1 1 k d b dc fp k d b 125 m s rb1 rb2 tb8 rd1 td1 td2 rk twf 11 d b dc wave shape of line signal r1n r2n receive receive data sync clk1 fhw bhw clk2 clk3 fd bd fk t1n t2n transmit transmit data figure 5
? semiconductor MSM7503 29/41 functional description control data description sounder calling tone and tone on/off control write mode address data ad1 = 0, ad0 = 0 db7 sounder output on sw19 on sw15 off, db6 db5 db4 db3 db2 db1 db0 control data description for control remarks 1 0 1 0 1 0 1 0 1 0 00 00 01 01 10 10 11 11 11 11 00 0 00 0 1 sounder output off sw19 off sounder output on sw20 on sounder output off sw20 off r-tone on sw13 on r-tone off sw13 off f-tone on(1 khz) sw14 on, sw15 off, f-tone off sw14 off, sw15 on, f-tone on(1 khz) sw14 off, sw15 off, f-tone off sw14 off, tone output: sa0 tone output: spo *1 tone output: rpo tone output: spo *1: this sounder output is sent at the timing shown below. on off on off 0.25 s 0.125 s 0.625 s 2 s
? semiconductor MSM7503 30/41 level and frequency control of sounder and r-tone write mode address data ad1 = 0, ad0 = 0 db7 sa0 output sounder volume 1 (large) db6 db5 db4 db3 db2 db1 db0 control data description for control remarks 0 00 01 10 11 01 00 0 sa0 output sounder volume 2 (middle) sa0 output sounder volume 3 (small 1) sa0 output sounder volume 4 (small 2) sounder combination tone 1 (16 hz wamble tone with 1000 hz/1333 hz) sounder combination tone 2 (16 hz wamble tone with 667 hz/800 hz) sounder combination tone 3 (8 hz wamble tone with 800 hz/1000 hz) sounder combination tone 4 (single tone of 1000 hz) sounder combination tone 5 (single tone of 800 hz) sounder combination tone 6 (single tone of 400 hz) sounder volume and tone are defind at a time. 01 0 10 0 00 1 01 1 10 1 r-tone output level 1 (90 mv pp at rpo output) 1 00 01 10 11 00 0 r-tone output level 2 (120 mv pp at rpo output) r-tone output level 3 (150 mv pp at rpo output) r-tone output level 4 (180 mv pp at rpo output) r-tone 400 hz single tone r-tone 425 hz single tone r-tone 440 hz single tone r-tone 450 hz single tone r-tone 400 hz on/off by 16 hz r-tone 400 hz on/off by 20 hz 01 0 10 0 11 0 00 1 01 1 at the initial setting, sounder volume 1 and sounder combination tone 1 are set. sa0 sounder volume: vol 13 r-tone output level = vol 7 r-tone output level and frequency are defined at a time. at the initial setting, output level 1 and a single 400 hz tone are set.
? semiconductor MSM7503 31/41 pb tone control write mode address data ad1 = 0, ad0 = 0 db7 db6 db5 db4 db3 db2 db1 db0 control data remarks 00 01 10 11 10 01 when pbtc = 0 sw16: on sw17: on sw18: off 01 01 01 10 10 10 11 00 01 11 11 xx 00 00 00 00 10 10 11 11 00 01 10 11 00 01 10 11 xx pb 1 2 3 a 9 c * 0 4 5 6 b 7 8 # d pb tone stop high low 1209 hz 697 hz 1336 697 1477 697 1633 697 1209 770 1336 770 1477 770 1633 770 1209 852 1336 852 1477 852 1633 852 1209 941 1336 941 1477 941 1633 941 output pb frequency sw16, sw17, sw18: off 00 1 pbtc pb tone is sent to the transmit path t0 and the receive path rpo. when pbtc = 1 sw16: off sw17: off sw18: on pb tone is sent to the receive path spo only.
? semiconductor MSM7503 32/41 sw control and timer reset write mode address data ad1 = 0, ad0 = 0 db7 sw1 db6 db5 db4 db3 db2 db1 db0 control data description for control remarks 1 01 10 11 01 11 0 when hold tone or pb tone transmit is selected, these inputs are muted. 01 01 10 10 10 11 00 01 10 11 above codes 00 00 01 00 00 00 10 11 11 11 10 11 00 01 10 11 00 00 on transmit handfree input sw2 on transmit handset input sw3 on receive input sw4 on side tone input sw5 on receive main amplifier input sw6 on receive speaker input sw7 on transmit path hold tone input sw8 on receive path hold tone acknowledge input sw9 on additional receive input sw10 on additional speaker input sw11 on speaker dec input sw12 on pcm output enable la = 1 lb = 1 general latch output for external control above corresponding sw or latch is set to off or "0". 00 0 0 all of above sws or latches are set to off or "0" at the initial setting stage. 1 1 watchdog timer is reset. 11 when handfree input is selected, side tone is muted. speaker dec input = codec aout
? semiconductor MSM7503 33/41 gain setting (receive gain, side tone gain) write mode address data ad1 = 0, ad0 = 0 db7 typical receive gain (C6db) db6 db5 db4 db3 db2 db1 db0 control data description for control remarks 00 01 10 11 00 1 C8 db than the typical gain typical side tone gain (C9 db) receive gain = vol1 1 1 1 0 1 1 1 0 0 0 0 00 01 10 11 0 0 1 0 0 1 1 1 0 0 1 0 0 0 0 0 1 1 1 1 C6 db than the typical gain C4 db than the typical gain C2 db than the typical gain +2 db than the typical gain +4 db than the typical gain +6 db than the typical gain C12 db than the typical gain C9 db than the typical gain C6 db than the typical gain C3 db than the typical gain +3 db than the typical gain +6 db than the typical gain side tone off (vol2 max loss) side tone gain = vol2 receive gain and side tone gain are set at a time. at the initial setting, the typical gain is set.
? semiconductor MSM7503 34/41 gain control (transmit hold tone, pb tone, microphone input, handset input) write mode address data ad1 = 0, ad0 = 1 db7 typical transmit hold tone gain (C2 db) db6 db5 db4 db3 db2 db1 db0 control data description for control remarks 0 00 01 10 11 01 00 0 C3 db with respect to the typical gain transmit hold tone gain = vol3 01 10 11 1 10 11 10 11 01 00 01 00 C6 db with respect to the typical gain C9 db with respect to the typical gain typical transmit pb tone gain (+4 db) C3 db with respect to the typical gain C6 db with respect to the typical gain C9 db with respect to the typical gain typical handfree input gain (+20 db) C6 db with respect to the typical gain C9 db with respect to the typical gain typical handset input gain (+12 db) C3 db with respect to the typical gain C6 db with respect to the typical gain C9 db with respect to the typical gain transmit pb tone gain = vol4 hold tone gain and pb tone gain are set at a time. at the initial setting, the typical gain is set. handfree input gain = vol9 handset input gain = vol8 handfree input gain and handset input gain are set at a time. at the initial setting, the typical gain is set.
? semiconductor MSM7503 35/41 gain control (receive pad, speaker) write mode address data ad1 = 0, ad0 = 1 db7 typical speaker pre-amp. gain (0 db) db6 db5 db4 db3 db2 db1 db0 control data description for control remarks 1 00 01 10 11 10 1 -4 db with respect to the typical gain speaker pre-amp. gain = vol5 1 1 1 0 0 1 0 0 0 0 1 0 00 01 0 0 0 0 00 01 10 11 0 1 1 1 00 01 10 11 10 0 0 0 0 1 1 -8 db with respect to the typical gain -12 db with respect to the typical gain -16 db with respect to the typical gain -20 db with respect to the typical gain -24 db with respect to the typical gain -28 db with respect to the typical gain typical additional speaker input path gain (0 db) -6 db with respect to the typical gain -12 db with respect to the typical gain -18 db with respect to the typical gain speaker receive off(sw21 off) speaker receive on (sw21 on) typical receive pad gain (0 db) -3 db with respect to the typical gain -6 db with respect to the typical gain -9 db with respect to the typical gain typical incoming tone gain (0 db) -10 db with respect to the typical gain -20 db with respect to the typical gain additional speaker gain = vol6 speaker pre-amp. gain and additional speaker gain are set at a time. at the initial setting, sw21-off and the typical gain are set. receive pad = vol10 incoming tone gain = vol11, vol12 receive pad and incoming tone gain are set at a time. at the initial setting, the typical gain is set.
? semiconductor MSM7503 36/41 key scanning signal output control write mode address data ad1 = 1, ad0 = 0 db7 the data set on db7 to db0 are output on po7 to po0 respectively. output data is held until next data is written. when the set data is set to "0", output data goes to "0", when set to "1", output pin is left open. at the initial setting, po7 to po0 are in open state. db6 db5 db4 db3 db2 db1 db0 controlo data description for control output data key scanning data read out read mode address data ad1 = 1, ad0 = 0 db7 data input onto pi7 to pi0 are output onto db7 to db0. db6 db5 db4 db3 db2 db1 db0 contorol data description for control pi7 pi6 pi5 pi4 pi3 pi2 pi1 pi0
? semiconductor MSM7503 37/41 special functions write mode address data ad1 = 1, ad0 = 1 db7 vlcd pin output voltage : 0.0 v db6 db5 db4 db3 db2 db1 db0 contorol data description for control remarks lcd deflection angle control voltage output 000 001 010 011 100 101 110 111 01000 : 0.20 v : 0.40 v : 0.60 v : 0.8 v : 1.0 v : 1.2 v : 1.4 v at the initial setting stage, set to 0 v. power down mode control analog, codec power down mode 00 01 10 11 analog, codec power on mode codec power down mode codec power on mode 100000 at the initial setting stage, set to analog and codec power down mode. codec power on/off control is valid in the analog and codec power on m ode. codec control codec operates in m -law 0 1 0 1 codec operates in a-law fhw and bhw are normally connected bhw is connected to fhw 110000 at the initial setting stage, set to m -law, and fhw and bhw are normally connected. the componding law and the connection control are set at a time. *2: even during the analog and codec power down mode, following functions are available, key scanning data i/o, sounder outputs (sa0), wdt, and general latch output (la, lb)
? semiconductor MSM7503 38/41 application circuit controller hold tone generator *1 *2 100 k w speaker sgt tpai cao r1i rpo rmi rmo0 rmo1 spo spi sao 100 k w 0.1 m f 100 k w 0.1 m f +5 v 0 v 0.1 m f to 1 m f 0.1 m f 10 m f + +5 v r1n mpai tpao tpbi mpbi mpbo mpao to cai mldyi po0 po1 po2 po3 po4 po5 po6 po7 p i 0 p i 1 p i 2 p i 3 p i 4 p i 5 p i 6 p i 7 s g c a g d g c t e s t t e s t sw matrix mic input line r2n t1n t2n +5 v +5 v +5 v +5 v ps lrstn wrn rdn cen db0 to db7 ad0 ad1 clk2 clk3 bd bds fk v d v a x1 x2 fd clc 100 k w handset *1 inserting a capacitor (1 to 22 m f) between sgt and ag will inprove the transmit path noise characteristics *2 insert a resistor if necessary 0-10 w
? semiconductor MSM7503 39/41 MSM7503 speech path level setting tpao mldyi to cai tpbi mpao mpai + C 20 db ain aout codec rmo0 r1i cao tpai spo rmo1 mpbi mpbo r2i 0 db spi sw5 sw5 sw1 sw2 sw7 sw16 5.7 db 0 db vol 3 vol 4 rpo rmi sw21 sw20 sw11 sw15 vol 5 vol 12 vol 11 C 22 db sw18 C 6.8 db sw10 vol 6 sw8 C 3 db sw6 0 db sw3 vol 1 sw4 vol 2 sw13 vol 7 sw17 C 8.7 db sw14 0 db sw9 0 db C 20 db to +25 db variable range step width typical level vol no. C14 db to 0 db C21 db to C3 db C11 db to C2 db C5 db to +4 db C28 db to 0 db C6 db C9 db C2 db +4 db 0 db 0 db 0 db +12 db +20 db 0 db 0 db 0 db vol 6 vol 7 vol 8 vol 9 vol 10 vol 11 vol 12 vol 1 vol 2 vol 3 vol 4 vol 5 C18 db to 0 db 90 mv to 180 mv +3 db to +12 db +11 db to +20 db C9 db to 0 db C20 db to 0 db C20 db to 0 db 2 db 3 db 3 db 3 db 4 db 6 db 30 mv 3 db 3,6 db 3 db 10 db 10 db vol 10 vol 9 vol 8 C + + C C C codec i/o level overload point: 1.2 v op 0 dbmo : 0.6007 vrms (C4.4 dbv) pb gen. per wave 0.24 v pp (C21.4 dbv equivalent) r-tone gen. 90 mv pp pulse (C27.8 dbv equivalent) f-tone gen. 0.16 v pp pulse (C22.8 dbv equivalent) s-tone gen. 0.22 v pp pulse (C20.0 dbv equivalent) C C C C + : the output signal is input with the same phase as : the output signal is with inverted phase. note :
? semiconductor MSM7503 40/41 recommendations for actual design ? to assure proper electrical characteristics, use bypass capacitors with excellent high frequency characteristics for the power supply and keep them as close as possible to the va and ag pins. ? connect the ag pin and the dg pin each other as close as possible. connected to the system ground with low impedance. if the ag and dg of the device are connected to different ground lines, the device may be latched up. ? connect the va pin and the vd pin as close together as possible and routed them to the analog 5 v power supply. if the va and vd of the device are connected to different power supplies, the device may be latched up. ? mount the device directly on the board when mounted on pcbs. do not use ic sockets. if an ic socket is unavoidable, the short lead type socket is recommended. ? when mounted on a frame, electro-magnetic shielding should be recommended, if any electro- magnetic wave source such as power supply transformers is surrounding the device. ? keep the voltage on the v dd pin not lower than C0.3 v even instantaneously to avoid latch-up phenomenon when turning the power on. ? use a low noise (particularly, low level type of high frequency spike noise or pulse noise) power supply should be used to avoid the erroneous operation and the degradation of the characteristics of these devices. ? connect analog input pins and digital input pins that are not used to the sg pin and to gnd, respectively. ? when the data is written differently from the data defined in the section, control data description in functional description, the device is not guaranteed in normal operation.
? semiconductor MSM7503 41/41 (unit : mm) package dimensions notes for mounting the surface mount type package the sop, qfp, tsop, soj, qfj (plcc), shp and bga are surface mount type packages, which are very susceptible to heat in reflow mounting and humidity absorbed in storage. therefore, before you perform reflow mounting, contact okis responsible sales person for the product name, package name, pin number, package code and desired mounting conditions (reflow method, temperature and times). qfp80-p-1420-0.80-bk package material lead frame material pin treatment solder plate thickness package weight (g) epoxy resin 42 alloy solder plating 5 m m or more 1.27 typ. mirror finish

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